? semiconductor components industries, llc, 2012 march, 2012 ? rev. 6 1 publication order number: NB3N853531E/d NB3N853531E 3.3 v xtal or lvttl/lvcmos input 2:1 mux to 1:4 lvpecl fanout buffer description the NB3N853531E is a low skew 3.3 v supply 1:4 clock distribution fanout buffer. an input mux selects either a fundamental parallel mode crystal or a lvcmos/lvttl clock by using the clk_sel pin (high for crystal, low for clock) with lvcmos / lvttl levels. the single ended clk input is translated to four lvpecl outputs. using the crystal input, the NB3N853531E can be a clock generator. a clk_en pin can enable or disable the outputs synchronously to eliminate runt pulses using l vcmos/lvttl levels (high to enable outputs, low to disable outputs). features ? four differential 3.3 v lvpecl outputs ? selectable crystal or lvcmos/lvttl clock inputs ? up to 266 mhz clock operation ? output to output skew: 30 ps (max) ? device to device skew 200 ps (max) ? propagation delay 1.8 ns (max) ? operating range: v cc = 3.3 5% v( 3.135 to 3.465 v) ? additive phase jitter, rms: 0.053 ps (typ) ? synchronous clock enable control ? industrial temp. range ( ? 40 c to 85 c) ? pb ? free tssop ? 20 package ? ambient operating temperature range ? 40 c to +85 c ? these are pb ? free devices figure 1. simpl i fied logic diagram osc pullup clk_en pulldown clk xtal_in xtal_out pulldown 1 0 d q q0 q0 q1 q1 q2 q2 q3 q3 clk_sel marking diagram a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information tssop ? 20 dt suffix case 948e nb3n 531e alyw
NB3N853531E http://onsemi.com 2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q0 q0 v cc q1 q1 q2 q2 v cc q3 q3 v ee clk_en clk_sel nc xtal_in xtal_out nc nc v cc clk figure 2. pinout diagram (top view) table 1. pin description pin name i/o open de- fault description 1 v ee negative (ground) power supply pin must be externally connected to power supply to guarantee proper operation. 2 clk_en lvcmos / lvttl pullup synchronized clock enable when high. when low, outputs are disabled (qx high, qx low) 3 clk_sel lvcmos / lvttl pulldown clock input select (high selects crystal, low selects clk input) 4 clk lvcmos / lvttl pulldown clock input. float open when unused. 5, 8, 9 nc no connect 6 xtal_in crystal crystal oscillator input (used with pin 7). float open when unused. 7 xtal_out crystal crystal oscillator output (used with pin 6). float open when unused. 10, 13, 18 v cc positive power supply pins must be externally connected to power supply to guarantee proper operation. 11, 14, 16, 19 q[3:0] lvpecl complement differential outputs (see and8020 for termination) 12, 15, 17, 20 q[3:0] lvpecl true differential outputs (see and8020 for termination) table 2. functions inputs outputs clk_en clk_sel input function output function qx qx 0 0 clk input selected disabled low high 0 1 crystal inputs selected disabled low high 1 0 clk input selected enabled clk0 invert of clk1 1 1 crystal inputs selected enabled clk1 invert of clk1 1. after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in f igure 3.
NB3N853531E http://onsemi.com 3 figure 3. clk_en timing diagram clk clk_en enabled disabled q[0:3] q[0:3] table 3. attributes (note 2) characteristics value internal input pullup resistor 50 k internal input pulldown resistor 50 k c in input capacitance 4 pf esd protection human body model machine model > 2 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 2) level 1 flammability rating oxygen index ul 94 v ? 0 @ 0.125 in 28 to 34 transistor count 333 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 4. maximum ratings (note 3) symbol parameter condition 1 condition 2 rating unit v cc supply voltage 4.6 v v in input voltage ? 0.5 v i vcc + 0.5 v i out output current continuous surge 50 100 ma t a operating temperature range, industrial ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm single ? layer pcb (700 mm 2 , 2 oz) 128 c/w 200 lfpm multi ? layer pcb (700 mm 2 , 2 oz) 94 jc thermal resistance (junction ? to ? case) (note 4) tssop ? 20 23 to 41 c/w t sol wave solder 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
NB3N853531E http://onsemi.com 4 table 5. crystal characteristics and connections parameter min typ max unit mode of oscillation fundamental parallel frequency 12 40 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive level 1 mw table 6. dc characteristics v cc = 3.3 5% v (3.135 to 3.465 v), v ee = 0 v, t a = ? 40 c to +85 c (note 5) symbol characteristic min typ max unit i ee power supply current 60 ma v ih input high voltage 2 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v i ih input high current (v cc = 3.456 v) clk, clk_sel = 3.456 v clk_en = 3.456 v 150 5 a i il input low current (v cc = 3.456 v) clk, clk_sel = 3.456 v clk_en = 3.456 v ? 5 ? 150 a v oh output high voltage v cc ? 1.4 v cc ? 0.9 v v ol output low voltage v cc ? 2.0 v cc ? 1.7 v vout swing output voltage swing (peak ? to ? peak) 0.6 1.0 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. outputs terminated 50 to v cc ? 2.0 v, see figure 4. table 7. ac characteristics v cc = 3.3 5% v (3.135 to 3.465 v), v ee = 0 v, ta = ? 40 c to +85 c (note 6) symbol characteristic min typ max unit f max maximum operating frequency 0 266 mhz t pd propagation delay (notes 7 and 9) 1.1 1.8 ns tskew dc duty cycle skew same path similar conditions at 50 mhz (notes 7, 8 and 9) 46 54 % tskew o ? o output to output skew within a device (notes 7, 8 and 9) 30 ps tskew d ? d device to device skew similar path and conditions (notes 7, 8 and 9) 200 ps t jit additive phase noise jitter (rms) @ 155.52 mhz (integrated from 12 khz to 20 mhz) see figure 6. (note 9) 0.053 ps t r /t f output rise and fall times (20% and 80% points) (note 9) 225 600 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. outputs terminated 50 to v cc ? 2.0 v, see figure 4. 7. measured under the same supply voltage, output loading, and input conditions. 8. similar conditions. 9. limits do not apply to overdriving xtal_in.
NB3N853531E http://onsemi.com 5 figure 4. typical test setup and termination for evaluation. a split supply of v cc = 2.0 v and v ee = ? 1.3 0.165 v allows a convenient direct connection termination into typical oscilloscope 50 to gnd impedance modules. for application termination schemes see and8020. z o = 50 z o = 50 2 v ? 1.3 0.165 v 50 50 qx qx lvpecl v ee v cc figure 5. ac measurement reference v cc /2 v cc /2 input output 20% t pd t pd 20% 80% 80% t r t f propagation delay t pd duty cycle skew ? t skewdc t pw t period output tskew dc % t pw t period 100 tskew 0 ? 0 tskew 0 ? 0 input clkx clky output ? to ? output skew tskew 0 ? 0 tskew d ? d tskew d ? d input part #1 part #2 output output device ? to ? device skew, tskew d ? d
NB3N853531E http://onsemi.com 6 figure 6. for 155.52 mhz carrier, the NB3N853531E additive phase noise (dbc/hz) verses ssb offset frequency (hz) integrated jitter from 12 khz to 20 mhz (upper heavy line) is 88.1 fs rms. the e8663b source generator additive phase noise (lower light line) is 70.1 fs rms. where t jit = (t jitoutput ) 2 ? (t jitinput ) 2 = 53 fs NB3N853531E source generator application ? crystal input interface figure 7 shows the NB3N853531E device crystal oscillator interface using a typical parallel resonant crystal. a parallel crystal with loading capacitance c l = 18 pf could use series load caps c1 = 32 pf and c2 = 32 pf as nominal values, after subtracting a typical 4 pf of stray cap per line. the frequency accuracy and duty cycle skew can be fine tuned by adjusting the c1 and c2 values. for example, increasing the c1 and c2 values will reduce the operational frequency. note r1 is optional and may be 0 . figure 7. NB3N853531E crystal oscillator interface *r1 is optional. assuming 4 pf stray cap per pin. 32 pf 32 pf c1 c2 xtal_in/clk xtal_out r1* x1 18 pf parallel resonant crystal
NB3N853531E http://onsemi.com 7 figure 8. NB3N853531E phase noise with 25 mhz crystal ordering information device package shipping ? NB3N853531Edtg tssop ? 20 (pb ? free) 75 units / rail NB3N853531Edtr2g tssop ? 20 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3N853531E http://onsemi.com 8 package dimensions tssop ? 20 case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NB3N853531E http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3N853531E/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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